Continuous Compliance Pipeline
Project: Inverter_Core_MCU · Target: ASIL D / CAL 4
Current Release
v4.2.1-rc3
Commit: a8f9e2b (norxs-ci)
Build Success Rate
0%
Last 30 days
MISRA C Deviations
0
MISRA Compliance:2020 deviation process
SBOM Critical CVEs
0
System cleared for OTA
Automated Verification Flow
ISO 26262-6 & UN R155
Source & Build
Git Fetch
Cross-compile (ARM)
Cross-compile (ARM)
Static Analysis
Polyspace SAST
MISRA C:2023
MISRA C:2023
SIL Verification
Model-in-Loop
Unit Test (MC/DC)
Unit Test (MC/DC)
HIL / Dyno Test
dSPACE Simulation
Fault Injection
Fault Injection
Sign-off & OTA
Generate Artifacts
SecOC Signing
SecOC Signing
bash - norxs_ci_runner.sh
System ready. Waiting for trigger...
Structural Coverage — Unit Level (ISO 26262-6, Table 12 · ASIL D)
MC/DC gap covered by deviation justification DR-051 (defensive
branches unreachable by design) — reviewed per ISO 26262-8 §9.
SBOM Vulnerability Scanner 🛡️ UN R155
CVE-2023-0464
OpenSSL 3.0.8 (Zone 3 IVI) · CVSS 7.5
Patched in 3.0.9
CVE-2020-22283
lwIP 2.1.2 (BMS comms) · CVSS 7.5
VEX: Not Exploitable (IPv6 disabled)
SAST Results — Polyspace Static Analysis
Run #0| Rule | Severity | File / Location | Description | Disposition |
|---|
Tool Qualification — ISO 26262-8 §11
TCL Register| Tool | Use Case | TI | TD | TCL | Qualification Method |
|---|
Load your own pipeline evidence
LCOV / SARIF · in-browserDrop an LCOV tracefile from gcov or llvm-cov, or a SARIF log from your MISRA checker, and the coverage and static-analysis panels are rebuilt from it. Parsed in this browser; a SARIF log names your source files and line numbers.
Drop an LCOV .info or SARIF .json file hereor click to choose · .info, .json, .sarif